// testTinyComp
// TinyComp test script

`timescale 1ns / 1ps 
module testTinyComp;

   reg 		Ph0In, Ph1In; //clock phases 
   reg 		Reset;
   reg [31:00] InData; // I/O input 
   reg 		InRdy;
   wire 	InStrobe; //executing an Input instruction 
   wire 	OutStrobe; // executing an Output instruction 
   
   TinyComp tinyComp1 (Ph0In, Ph1In, Reset, InData, InRdy, InStrobe, OutStrobe);

   parameter PERIOD = 1;

   initial begin
      Ph0In = 1'b0;
      Ph1In = 1'b0;
      Reset = 1'b0;
      #5 Reset = 1'b1;
      #5 Reset = 1'b0;
   end

   // clock
   always begin
      #(PERIOD) Ph0In = 1'b1;
      #(PERIOD) Ph1In = 1'b1;
      #(PERIOD) Ph0In = 1'b0;
      #(PERIOD) Ph1In = 1'b0;
   end
   
   initial
     // debugging
     $monitor($stime, " :: Reset=%b Ph0In=%b Ph1In=%b", Reset, Ph0In, Ph1In);
    
endmodule    

module ramx(
	    input clkb,
	    input [9:0] addrb,
	    output reg [31:00] doutb,
	    input clka,
	    input [9:0] addra,
	    input wea,
	    output reg [31:00] dina
	    );
   always @(posedge clka) doutb = 0;
   always @(posedge clkb) dina = 0;
   
endmodule // ramx